Diodes are semiconductor devices characterized by the ability to block high voltage in the reverse direction with very low leakage current and carry high current in the forward direction with low forward voltage drop. They can be of two different types, either P—N or Schottky diodes. P—N diodes are made of two oppositely doped semiconductor portions, which form a P—N electrical junction. Typically, the P—N junction is formed by implanting doped wells into an oppositely doped semiconductor substrate. Schottky diodes are made of a metal region and a semiconductor region, with the difference in work-function between the two regions forming a Schottky electrical junction. Typically, the Schottky junction is formed by depositing a metal on a doped semiconductor substrate. Both types of diodes are widely used in power electronic circuits to provide the functions for freewheeling, rectification, and snubbing in converters, inverters, motor controls, switch mode power suppliers, power factor correction, inductive heating, welding, uninterruptible power supplies and many other power conversion applications.
Silicon has been and remains the material of choice to manufacture semiconductor devices. Technology improvement enabled a steady reduction of silicon devices cost over the years. However, in the field of power electronics, new materials such as silicon carbide (SiC) could compete with silicon. Recent break-throughs in SiC technology allow to take full advantage of SiC better high voltage (critical avalanche electric field) and high temperature (thermal conductivity) characteristics than silicon.
Typically, the fabrication process of high performance, high blocking voltage fast rectifying diodes require four to six photomasks for the implementation of all desired features. In the prior art, a minimum of three photomasks for silicon technology and four photomasks for SiC technology were reported. FIGS. 1A-1D illustrate steps of a prior art three photomask fabrication process of a fast recovery epitaxial diode (FRED) in silicon technology.
In a first step, illustrated in FIG. 1A, a field layer 10, typically consisting of silicon dioxide, is grown on a semiconductor layer 20 and a first photomask (not shown) is used to etch field layer 10. The term ‘field layer’, as used herein, and as known to those skilled in the art at the time of the invention, means a patterned layer which protects a high voltage termination of a semiconductor device. Windows 15 are etched in field layer 10. In one embodiment, semiconductor layer 20 consists of an n-doped semiconductor. Particularly, in one further embodiment, semiconductor layer comprises: an epitaxial layer 30 exhibiting a first face 32 and a second face 34, second face 34 opposing first face 32; and a doped substrate 40 exhibiting a first face 42 and a second face 44, second face 44 opposing first face 42. First face 32 of epitaxial layer 30 is deposited on first face 42 of doped substrate 40 and field layer 10 is grown on second face 34 of epitaxial layer 30. Additionally, field layer 10 exhibits a first face 12 and a second face 14, second face 14 opposing first face 12. First face 12 of field layer 10 faces second face 34 of epitaxial layer 30.
In a second step, illustrated in FIG. 1B, dopant ions are implanted into epitaxial layer 30, through windows 15, and diffused into the desired depth, to form doped wells 50. The doping of doped wells 50 is the opposite of the doping of semiconductor layer 20. Particularly, in the event that semiconductor layer 20 is doped with an n-type dopant, doped wells 50 are formed with a p-type dopant, and vice versa. The diffusion and activation of doped wells 50 are performed at high temperatures, up to 1200° C. for silicon technology. The doping level and depth of doped wells 50 are varied dependent upon the desired blocking voltage and the particular voltage blocking scheme.
In a third step, illustrated in FIG. 1C, a metal layer 60 is deposited onto second face 34 of epitaxial layer 30. Particularly, metal layer 60 fills in windows 15 to cover doped wells 50 and additionally covers a portion of second face 14 of field layer 10. A second photomask (not shown) is used to etch metal layer 60 to expose portions of field layer 10.
In a fourth step, illustrated in FIG. 1D, a passivation layer 70 is deposited over field layer 10. A third photomask (not shown) is used to etch passivation layer 70 to expose a portion of metal layer 60. In one embodiment, passivation layer 70 consists of silicon oxynitride. Passivation layer 70 is used due to the fact that the silicon dioxide of field layer 10 does not block the diffusion of mobile ions. Particularly, mobile ions, such as sodium and potassium, accumulate on second face 14 of field layer 10. The mobile ions diffuse into field layer 10 and travel to the junction between first face 12 of field layer 10 and second face 34 of epitaxial layer 34, where they attract electrons from semiconductor layer 20. The blocking voltage of the diode thereby changes due to voltages and currents generated at second face 34 of epitaxial layer 30 by the diffused mobile ions. In diodes with a high blocking voltage, which exhibit low doping concentrations of semiconductor layer 20, the effects are very significant since even low amounts of mobile ions will have a significant effect on the charges in the low doped semiconductor layer 20. The diffusion of the mobile ions into field layer 10 increases responsive to the electric field generated when a voltage is present across the diode. Additionally, the diffusion of the mobile ions into field layer 10 increases exponentially responsive to an increase in temperature. Specifically, the diffusivity of field layer 10, denoted D, is given as:D=D0*e−EA/(kT)  EQ. 1where D0 is the maximal diffusion coefficient, EA is the diffusion activation energy, k is the Boltzmann constant and T is the absolute temperature. As shown in EQ. 1, the diffusion coefficient is an exponential function of the temperature.
Passivation layer 70 consists of material which effectively blocks the mobile ions from reaching field layer 10, thereby preventing any diffusion of those mobile ions into field layer 10. Unfortunately, depositing and etching passivation layer 70 requires an additional photomask, which adds cost and complexity to the fabrication process. Although the above has been described in relation to the fabrication process of a FRED, the additional photomask for a passivation layer is needed in other types of diodes, such as an SiC Schottky barrier diode (SBD), as will be described below.
A SiC SBD fabrication process requires one additional photomask compared to a silicon FRED process. The activation of the doped wells in SiC is performed at temperatures up to 1700° C. At such temperature, no known field layer material would keep its structural integrity. Therefore, the field layer patterning and dopant implantation cannot share the same photomask and each step should have a dedicated photomask. The dopant implantation is performed first. A subsequent clean up provides a bare SiC surface to move to the dopant activation step. Once the dopant activation is completed, the field layer can be deposited and patterned.
What is desired, and not provided by the prior art, is a method of fabricating a semiconductor device without the need of additional photomask for a passivation layer.